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Studies on DFT for reducing its area and test application time of system-on-a-chip
https://doi.org/10.34413/dr.00568
https://doi.org/10.34413/dr.0056851760311-78d9-4bb2-a262-2ddff4587d86
名前 / ファイル | ライセンス | アクション |
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fulltext (537.8 kB)
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abstract (214.8 kB)
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Item type | 学位論文(博士論文) / Thesis or Dissertation(1) | |||||
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公開日 | 2006-07-31 | |||||
タイトル | ||||||
タイトル | Studies on DFT for reducing its area and test application time of system-on-a-chip | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | SoC | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | test scheduling | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | test access mechanism | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | wrapper | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | design for test | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | memory BIST | |||||
資源タイプ | ||||||
資源タイプ | doctoral thesis | |||||
その他のタイトル | ||||||
その他のタイトル | システムオンチップのテスト回路面積とテスト実行時間を低減するテスト容易化設計法に関する研究 | |||||
その他のタイトル | ||||||
その他のタイトル | システムオンチップ ノ テスト カイロ メンセキ ト テスト ジッコウ ジカン オ テイゲンスル テスト ヨウイカ セッケイホウ ニ カンスル ケンキュウ | |||||
著者 |
宮崎, 政英
× 宮崎, 政英 |
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書誌情報 |
発行日 2006-03-24 |
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出版者 | ||||||
出版者 | Nara Institute of Science and Technology | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
学位名 | ||||||
学位名 | 博士(工学) | |||||
学位授与機関 | ||||||
学位授与機関名 | 奈良先端科学技術大学院大学 | |||||
学位授与年月日 | ||||||
学位授与年月日 | 2006-03-24 | |||||
学位授与番号 | ||||||
学位授与番号 | 甲第568号 | |||||
電子化ID | ||||||
電子化ID |