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A New Design Approach for High-Throughput Arithmetic Circuits for Single-Flux-Quantum Microprocessors
http://hdl.handle.net/10131/4227
http://hdl.handle.net/10131/4227c42599e3-9b81-4be2-8c0c-c80d3031b9ae
名前 / ファイル | ライセンス | アクション |
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9_IEEE_2007_Tanaka.pdf (833.0 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2009-12-11 | |||||
タイトル | ||||||
タイトル | A New Design Approach for High-Throughput Arithmetic Circuits for Single-Flux-Quantum Microprocessors | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題 | arithmetic circuits, high throughput, microprocessor, single flux quantum (SFQ) logic | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Tanaka, M.
× Tanaka, M.× Yamanashi, Y.× Kamiya, Y.× Akimoto, A.× Irie, N.× Park, H.× Fujimaki, A.× Yoshikawa, N.× Terai, H.× Yorozu, S. |
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著者(ヨミ) | ||||||
識別子Scheme | WEKO | |||||
識別子 | 17303 | |||||
姓名 | ヨシカワ, ノブユキ | |||||
著者別名 | ||||||
識別子Scheme | WEKO | |||||
識別子 | 17304 | |||||
姓名 | 吉川, 信行 | |||||
著者所属 | ||||||
Nagoya University | ||||||
著者所属 | ||||||
Japan Society for the Promotion of Science | ||||||
著者所属 | ||||||
Yokohama National University | ||||||
著者所属 | ||||||
National Institute of Information and Communications Technology | ||||||
著者所属 | ||||||
Superconductivity Research Laboratory, International Superconductivity Technology Center | ||||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | We propose a new design approach for high-throughput arithmetic circuits based on state transitions using single-flux-quantum (SFQ) logic circuits. Microprocessors have several complex interconnects in datapath including loops of data, to which only one SFQ pulse is allowed to be confined, and the loops can spoil the high-throughput nature of SFQ circuits. In our new approach, we regard an arithmetic circuit with loops as a sequential logic circuit, and we use nondestructive readout gates (NDROs) as storage elements of the internal state. We can eliminate the loops and achieve high throughput by translating calculations into transitions of the state stored in the NDROs. We have implemented a bit-serial adder with the proposed approach, and demonstrated 36-GHz operations using the niobium 2.5-kA/cm(2) standard process technology. | |||||
書誌情報 |
IEEE transactions on applied superconductivity 巻 17, 号 2, Part 1, p. 516-519, 発行日 2007-06 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 10518223 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA10791666 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/TASC.2007.898714 | |||||
権利 | ||||||
権利情報 | ©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
フォーマット | ||||||
内容記述タイプ | Other | |||||
内容記述 | application/pdf | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronics Engineers |