Reed-Solomon codes encoder/decoder microprocessor based system

In this project, Reed-Solomon codes encoding and decoding algorithms are first discussed. A complete logic circuit design of the (255, 245) Reed-Solomon code encoder/decoder microprocessor based system is then presented. This code is defined over Galois Field GF (28) and has the capability or correcting up to five burst errors of 8 bits each or any burst combination of up to a total length of 40 bits provided they only affect a maximum of five individual symbols (bytes). For better efficiency, this design features a five-stage pipelined structured decoder which utilizes the parallelism in the decoding algorithm. Berlekamp's iterative algorithm is used to determine the coefficients of the error location polynomial, and Chien's searching algorithm is used to find its roots. In this design, only off the shelf integrated circuits are used. The Intel 8085 microprocessor has been utilized as a data processor in two of the decoder pipelined stages. Alternative design methods of various system parts have been investigated and speed and time delay measurements of these parts are included.