Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/84573| Author(s): | José S. Matos Filipe S. Pinto José M. M. Ferreira |
| Title: | A boundary scan test controller for hierarchical BIST |
| Issue Date: | 1992 |
| Abstract: | A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution. |
| Subject: | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática Electrical engineering, Electrical engineering, Electronic engineering, Information engineering |
| Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
| URI: | https://hdl.handle.net/10216/84573 |
| Source: | Proceedings of the IEEE International Test Conference |
| Document Type: | Artigo em Livro de Atas de Conferência Internacional |
| Rights: | openAccess |
| License: | https://creativecommons.org/licenses/by-nc/4.0/ |
| Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 53148.pdf | A Boundary Scan Test Controller for Hierarchical BIST | 384.62 kB | Adobe PDF |  View/Open |
This item is licensed under a Creative Commons License
