Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/80483
Title: Success rate model for fully AES-128 in correlation power analysis
Authors: Pammu, Ali Akbar
Chong, Kwen-Siong
Lwin, Ne Kyaw Zwa
Ho, Weng-Geng
Liu, Nan
Gwee, Bah Hwee
Keywords: AES-128
Correlation Power Analysis
Issue Date: 2016
Source: Pammu, A. A., Chong, K.-S., Lwin, N. K. Z., Ho, W.-G., Liu, N., & Gwee, B. H. (2016). Success rate model for fully AES-128 in correlation power analysis. 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 115-118.
Conference: 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Abstract: We propose a Success Rate (SR) estimation model for Correlation Power Analysis (CPA) attack on AES-128 encrypted devices. The SR is a ratio between the number of successful attacks to obtain secret key and the total number of attacks. There are two key features in the proposed model. First, we derive the Second Order Standard Deviation (SOSD) of the processed data to analyze their switching activities during encryption processes, to identify the Least Difficult Sub-Key (LDSK - the easiest revealable sub-key) and Most Difficult Sub-Key (MDSK - the hardest revealable sub-key). Second, we apply the Error Function Model (EFM) by using LDSK and MDSK to estimate the SR with respect to the number of power traces required to reveal the secret key. Our proposed SR estimation model is evaluated based on a Sukura-X encryption board and shows that our proposed SOSD requires only 1,000 processed data to determine the LDSK and MDSK. Based on the EFM of the LDSK and MDSK, it shows that 10%-94% of SR requires 1,220-3,550 power traces respectively to reveal all the 16 sub-keys. We demonstrate the accuracy of our proposed SR estimation model by benchmarking against the two reporting techniques to evaluate 1-byte of key and show that the accuracy of our technique is 96% whereas other reported techniques are only 21% and 49%.
URI: https://hdl.handle.net/10356/80483
http://hdl.handle.net/10220/42162
DOI: 10.1109/APCCAS.2016.7803910
Schools: School of Electrical and Electronic Engineering 
Research Centres: Centre for Integrated Circuits and Systems 
Rights: © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [https://doi.org/10.1109/APCCAS.2016.7803910].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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