Por favor, use este identificador para citar o enlazar a este item:
http://hdl.handle.net/10261/155901COMPARTIR / EXPORTAR:
 SHARE
BASE
|
|
| Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE | |
| Título: | Assessing application areas for tunnel transistor technologies |
Autor: | Avedillo, María J. CSIC ORCID; Núñez, Juan CSIC ORCID | Palabras clave: | Tunnel transistors Steep subthreshold slope Low power Energy efficiency Low supply voltage |
Fecha de publicación: | 2016 | Editor: | Institute of Electrical and Electronics Engineers | Citación: | Design of Circuits and Integrated Systems (DCIS), 2015 Conference, 25-27 November 2015 | Resumen: | Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas | Versión del editor: | https://doi.org/10.1109/DCIS.2015.7388581 | URI: | http://hdl.handle.net/10261/155901 | DOI: | 10.1109/DCIS.2015.7388581 |
| Aparece en las colecciones: | (IMSE-CNM) Comunicaciones congresos |
Ficheros en este ítem:
| Fichero | Descripción | Tamaño | Formato | |
|---|---|---|---|---|
| DCIS_CAMERA_2.pdf | 235,09 kB | Adobe PDF |  Visualizar/Abrir |
CORE Recommender
Page view(s)
245
checked on 19-abr-2024
Download(s)
240
checked on 19-abr-2024
Google ScholarTM
Check
Altmetric
Altmetric
NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.