Por favor, use este identificador para citar o enlazar a este item:
http://hdl.handle.net/10261/160006
COMPARTIR / EXPORTAR:
SHARE CORE BASE | |
Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE | |
Título: | An analyzable memory controller for hard real-time CMPs |
Autor: | Paolieri, Marco; Quiñones, Eduardo; Cazorla, Francisco J.; Valero, Mateo | Palabras clave: | Worst case execution time (WCET) CMP DDRx SDRAM Hard real-time Memory controller |
Fecha de publicación: | 2009 | Editor: | Institute of Electrical and Electronics Engineers | Citación: | IEEE Embedded Systems Letters 1: 86- 90 (2009) | Resumen: | Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources. We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations. © 2009 IEEE. | URI: | http://hdl.handle.net/10261/160006 | DOI: | 10.1109/LES.2010.2041634 | Identificadores: | doi: 10.1109/LES.2010.2041634 issn: 1943-0663 |
Aparece en las colecciones: | (IIIA) Artículos |
Ficheros en este ítem:
Fichero | Descripción | Tamaño | Formato | |
---|---|---|---|---|
accesoRestringido.pdf | 15,38 kB | Adobe PDF | Visualizar/Abrir |
CORE Recommender
SCOPUSTM
Citations
116
checked on 11-abr-2024
Page view(s)
206
checked on 18-abr-2024
Download(s)
62
checked on 18-abr-2024
Google ScholarTM
Check
Altmetric
Altmetric
NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.