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Título: | A programmable VLSI filter architecture for application in real-time vision processing systems |
Autor: | Serrano-Gotarredona, Teresa CSIC ORCID ; Andreou, A. G.; Linares-Barranco, Bernabé CSIC ORCID | Fecha de publicación: | 2000 | Editor: | World Scientific Publishing | Citación: | International Journal of Neural Systems 10(3): 179-190 (2000) | Resumen: | An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach is valid for any 2D filtering operation as long as the convolutional kernel F(p,q) is decomposable into an x-axis and a y-axis component, i.e. F(p,q)=H(p)V(q), for some rotated coordinate system [p,q]. If it is possible to find a coordinate system [p,q], rotated with respect to the absolute coordinate system a certain angle, for which the above decomposition is possible, then the proposed architecture is able to perform the filtering operation for any angle we would like the kernel to be rotated. This is achieved by taking advantage of the AER and manipulating the addresses in real time. The proposed architecture, however, requires one approximation: the product operation between the horizontal component H(p) and vertical component V(q) should be able to be approximated by a signed minimum operation without significant performance degradation. It is shown that for edge-extraction applications this filter does not produce performance degradation. The proposed architecture is intended to be used in a complete vision system known as the Boundary-Contour-System and Feature-Contour-System Vision Model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and electrical simulation and experimental results at the circuit level operation of some critical subcircuits. | Versión del editor: | http://dx.doi.org/10.1142/S0129065700000168 | URI: | http://hdl.handle.net/10261/84996 | DOI: | 10.1142/S0129065700000168 | Identificadores: | doi: 10.1142/S0129065700000168 issn: 0129-0657 e-issn: 1793-6462 |
Aparece en las colecciones: | (IMSE-CNM) Artículos |
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A programmable VLSI.pdf | 570,91 kB | Adobe PDF | Visualizar/Abrir |
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