Sub-1-V CMOS proportional-to-absolute temperature references

Abstract

This paper presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (μA) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-μW integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-μm very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+ > 60 dB. Hence, the resulting PTAT circuits are suitable for very-low voltage system-on-a-chip applications in digital CMOS technologies.