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https://hdl.handle.net/10356/3116
Title: | Design and optimization of a low-voltage CMOS circuit for portable applications | Authors: | Chan, Chee Chong. | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits | Issue Date: | 2003 | Abstract: | In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by replacing the dual ripple-carry adders with a carry skip adder for zero-carry in. | URI: | http://hdl.handle.net/10356/3116 | Schools: | School of Electrical and Electronic Engineering | Rights: | Nanyang Technological University | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Theses |
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File | Description | Size | Format | |
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EEE-THESES_101.pdf Restricted Access | 2.89 MB | Adobe PDF | View/Open |
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