A folded-switching mixer in SOI CMOS technology

Iji, A; Zhu, X; Heimlich, M

A folded-switching mixer in SOI CMOS technology

Iji, A Zhu, X

Heimlich, M

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Publication Type:: Conference Proceeding
Citation:: Midwest Symposium on Circuits and Systems, 2012, pp. 458 - 461
Issue Date:: 2012-10-16

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Field	Value	Language
dc.contributor.author	Iji, A	en_US
dc.contributor.author	Zhu, X https://orcid.org/0000-0002-5814-394X	en_US
dc.contributor.author	Heimlich, M	en_US
dc.date.issued	2012-10-16	en_US
dc.identifier.citation	Midwest Symposium on Circuits and Systems, 2012, pp. 458 - 461	en_US
dc.identifier.isbn	9781467325264	en_US
dc.identifier.issn	1548-3746	en_US
dc.identifier.uri	http://hdl.handle.net/10453/121239
dc.description.abstract	A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm 2. Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications. © 2012 IEEE.	en_US
dc.relation.ispartof	Midwest Symposium on Circuits and Systems	en_US
dc.relation.isbasedon	10.1109/MWSCAS.2012.6292056	en_US
dc.rights	info:eu-repo/semantics/closedAccess
dc.title	A folded-switching mixer in SOI CMOS technology	en_US
dc.type	Conference Proceeding
utslib.for	0906 Electrical and Electronic Engineering	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
pubs.organisational-group	/University of Technology Sydney/Strength - GBDTC - Global Big Data Technologies
utslib.copyright.status	closed_access	*
pubs.publication-status	Published	en_US

Abstract:

A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm 2. Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications. © 2012 IEEE.

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