A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs

Iji, A; Zhu, X; Heimlich, M

A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs

Iji, A Zhu, X

Heimlich, M

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Publication Type:: Conference Proceeding
Citation:: Midwest Symposium on Circuits and Systems, 2012, pp. 766 - 769
Issue Date:: 2012-10-16

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Field	Value	Language
dc.contributor.author	Iji, A	en_US
dc.contributor.author	Zhu, X https://orcid.org/0000-0002-5814-394X	en_US
dc.contributor.author	Heimlich, M	en_US
dc.date.issued	2012-10-16	en_US
dc.identifier.citation	Midwest Symposium on Circuits and Systems, 2012, pp. 766 - 769	en_US
dc.identifier.isbn	9781467325264	en_US
dc.identifier.issn	1548-3746	en_US
dc.identifier.uri	http://hdl.handle.net/10453/121241
dc.description.abstract	A low-voltage, low-power single-ended LNA is implemented in a 0.25μm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of -10 dBm and small-signal gain of 19.2 dB within the 3-5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm 2. Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs. © 2012 IEEE.	en_US
dc.relation.ispartof	Midwest Symposium on Circuits and Systems	en_US
dc.relation.isbasedon	10.1109/MWSCAS.2012.6292133	en_US
dc.rights	info:eu-repo/semantics/closedAccess
dc.title	A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs	en_US
dc.type	Conference Proceeding
utslib.for	0906 Electrical and Electronic Engineering	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
pubs.organisational-group	/University of Technology Sydney/Strength - GBDTC - Global Big Data Technologies
utslib.copyright.status	closed_access	*
pubs.publication-status	Published	en_US

Abstract:

A low-voltage, low-power single-ended LNA is implemented in a 0.25μm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of -10 dBm and small-signal gain of 19.2 dB within the 3-5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm 2. Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs. © 2012 IEEE.

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