Development of Algorithms and Architectures of Demodulator for Processing Satellite Data Communication

Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/119235

Title:	Development of Algorithms and Architectures of Demodulator for Processing Satellite Data Communication
Researcher:	K. R. Nataraj,
Guide(s):	Dr.B. S. Nagbushana
Keywords:	Algorithm, Distributed Arithmetic Architecture, Demodulator, Digital Frequency Synthesizer, Field Programmable Gate Array, Linear algebra, Quadrature Phase Shift Keying, Sampling Rate Converter, Transponder, Verilog and Matlab.
University:	Dr. M.G.R. Educational and Research Institute
Completed Date:	18/08/2010
Abstract:	newline
Pagination:
URI:	http://hdl.handle.net/10603/119235
Appears in Departments:	Department Of Electrical and Electronics Engineering

Files in This Item:

File	Description	Size	Format
bonafide.jpg	Attached File	640.99 kB	JPEG	View/Open
ch-1 introduction.pdf		51.33 kB	Adobe PDF	View/Open
ch-2 development of alogorithms for demodulator.pdf		213.74 kB	Adobe PDF	View/Open
ch-3 reciver structure and task participation.pdf		125.78 kB	Adobe PDF	View/Open
ch-4 implementationof sampling rate converter.pdf		424.31 kB	Adobe PDF	View/Open
ch-5 implementation of digital frequency synthesizer.pdf		128.79 kB	Adobe PDF	View/Open
ch-6 implementation of fpga part of the demodulator.pdf		25.93 kB	Adobe PDF	View/Open
ch-7 results of hardware demodulator.pdf		2.18 MB	Adobe PDF	View/Open
ch-8 conclusion and scope of future work, appendix.pdf		28.56 kB	Adobe PDF	View/Open
pretext.pdf		75.33 kB	Adobe PDF	View/Open