1. Shodhganga@INFLIBNET
  2. Dr. Rammanohar Lohia Avadh University, Faizabad
  3. Department of Physics and Electronics
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/228840
Title: Design Of High Speed Low Power Arithmetic Logic Unit Alu Using Logic Technique
Researcher: SHUKLA HANUMAN PRASAD
Guide(s): RIWARI RAJ KUMAR
Keywords: Design Of High Speed Low Power Arithmetic Logic Unit
University: Dr. Rammanohar Lohia Avadh University, Faizabad
Completed Date: 2011
Abstract: newline NO
Pagination: 284
URI: http://hdl.handle.net/10603/228840
Appears in Departments:Department of Physics and Electronics

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01_title.pdfAttached File345.59 kBAdobe PDFView/Open
02_certificate.pdf723.22 kBAdobe PDFView/Open
03_declaration.pdf223.75 kBAdobe PDFView/Open
04_acknowledgement.pdf812.87 kBAdobe PDFView/Open
05_preface.pdf2.14 MBAdobe PDFView/Open
06_index.pdf5.25 MBAdobe PDFView/Open
07_chapter1.pdf5.56 MBAdobe PDFView/Open
08_chapter2.pdf17.62 MBAdobe PDFView/Open
09_chapter3.pdf11.53 MBAdobe PDFView/Open
10_chapter4.pdf5.47 MBAdobe PDFView/Open
11_chapter5.pdf28.14 MBAdobe PDFView/Open
12_chapter6.pdf13.26 MBAdobe PDFView/Open
13_chapter7.pdf2.09 MBAdobe PDFView/Open
14_chapter8.pdf6.11 MBAdobe PDFView/Open
15_chapter9.pdf39.06 MBAdobe PDFView/Open
16_chapter10.pdf9.1 MBAdobe PDFView/Open
17_chapter11.pdf1.14 MBAdobe PDFView/Open
18_references.pdf33.55 MBAdobe PDFView/Open
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