Design of high speed reconfigurable co processor for next generation communication platform

Abstract

There has been an increasing demand on the quality of data transmission and reception newlineAs a result there has been an increase in bandwidth on demand and quality of service These results in increase of data traffic which results in information loss accuracy reduction and reliability reduction A coprocessor is designed to overcome this drawback which can be used for communication operation which is highly reliable and more accurate with less delay The research high speed reconfigurable coprocessor can be easily implemented using various standard operations such as Bit shuffle operation convolutional encoding fast Fourier transform interleaving modulation scrambling Shift XOR array viterbi decoding and many other functions which make use of the research design newline newline