SASC: A hardware string alignment coprocessor for stereo correspondence2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)

In this paper a design scheme is proposed for a hardware co-processor that, starting from a pair of stereo images, computes the “disparity map” between them used to define corresponding points on the two images. The followed approach, based on Dynamic Programming, is that proposed in a recent paper and exploits the well known Needleman & Wunsch's string-alignment algorithm used in bioinformatics. The architecture, highly modular, was designed using Bluespec System Verilog development tool and is described in detail. Synthesis results are shown for several FPGA platforms and demonstrates that the processor can result sufficiently small to be embedded in a totally hardware stereo images processing chain. Performance obtained and reported at the end of the paper show that the processor can run fast enough to be employed in real time instances.