A bi-dimensional filter for high accuracy image processing is implemented by using a novel partitioning method. The method is based on a number theory theorem, which permits to reduce the complexity of the operation to that of an adder chain and also the amount of the coefficients stored in memory, improving the memory organization. To show the advantage of such method, we implemented a Floating Point 32 (FP32) in hardware filtering applications and, in particular, for 2D FIR filters. Using Xilinx Virtex 7 Field Programmable Gate Array (FPGA) we obtain a critical path delay of 4.7ns which is comparable with the state-of-Art.

Hardware architecture for 2D Gaussian filtering of HD images on resource constrained platforms

Cappetta, Carmine;Licciardo, Gian Domenico;Di Benedetto, Luigi
Membro del Collaboration Group
2017-01-01

Abstract

A bi-dimensional filter for high accuracy image processing is implemented by using a novel partitioning method. The method is based on a number theory theorem, which permits to reduce the complexity of the operation to that of an adder chain and also the amount of the coefficients stored in memory, improving the memory organization. To show the advantage of such method, we implemented a Floating Point 32 (FP32) in hardware filtering applications and, in particular, for 2D FIR filters. Using Xilinx Virtex 7 Field Programmable Gate Array (FPGA) we obtain a critical path delay of 4.7ns which is comparable with the state-of-Art.
2017
9781538606742
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4700374
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