適用於無線視訊娛樂之多系統融合及節能技術---子計畫一：適用於多核心之低功率隨選記憶體系統(I)

Abstract

隨著多核心系統晶片的發展，多系統融合已成為必然的趨勢，因此，晶片上不僅需要放置更多、更快、且低功耗的記憶體來提供儲存資料，此記憶體也必須具備可以同時支援多個不同系統的能力，為此，我們提出一個隨選記憶體系統的構想。此隨選記憶體系統建構在多核心平台上，藉由記憶體管理單元的協助與管理，在此平台上執行之系統(多系統融合)將可以對記憶體快速地存取資料。隨選記憶體系統將包含分散式記憶體、共享式記憶體、記憶體匯流排和三層式記憶體管理單元;此外，我們也將結合子計畫二一同建立e-Home II(eH-II)之多核心平台，專司晶內資料傳遞及其通須協定之設計。我們將結合電路與架構的設計，提出管理晶片上動態記憶體分配、頻寬、與資料傳輸之機制，此外還負責管理晶片內外間資料傳輸之方法，且著重於低功耗之設計以解決多系統融合時所將遇到之瓶頸。另外，為了更有效率地管理功耗，我們將設計新的功率管理單元，並且使之與記憶體管理單元相整合。此外，我們也將研究低功率多執行序檔案暫存器，並將提出新的電路架構以減少檔案暫存器之面積與將低功率之消耗。最後，我們將利用SystemC建立所設計之記憶體系統的硬體模型，藉此縮短整合與驗證之時間，以即增加可重複使用性。我們將在第一年度研發記憶體元件的關鍵單元並完成階層式記憶體管理單元的架構建立。第二年度則完成多處理序暫存器設計以提供多核心單元快速存取暫存器，並且完成記憶體管理單元與記憶體匯流排之溝通。第三年則參酌其他子計畫的規格訂定來完成最後記憶體系統最終的細部架構，並且加入內建自我測試偵錯電路及內建自我修復電路；此外，將針對異質系統對於記憶體需求量不同，建構記憶體編譯程式，使其記憶體系統更完整。

Large amounts of high speed and low power memories are indispensable for multi-core platform and multi-system emerging. These memories should be able to support diverse systems, therefore, an on-demand memory system is proposed. This on-demand memory system provides high bandwidths and low power accesses for a multi-core platform by the memory management unit. On-demand memory system includes distributed memories, shared memories, memory bus, and three-layer memory management unit. Besides, we will establish e-Home II (eH-II) platform which is a multi-core platform with sub-project 2. We focus on the on-chip communication, data transfer, interfaces and protocols. With circuit and architecture designs, we will propose dynamic scheduling mechanisms for memory allocation, bandwidth, and on-chip data communication. In order to have better power control, we will provide novel power management unit and integrate it with the memory management unit. We will have further investigation on low power multi-thread register file and will provide novel circuit structure to reduce the area and power consumption of register files. Finally, we will use System C to construct our proposed on-demand memory system hardware model, so that to reduce integration and verification period and increase reusability. In the first year, we will develop key elements of memory units and complete the structure of multi-level memory management unit. In the second year, we will complete the multi-thread register file to provide multi-core units to access register files in high speed, and complete communication between memory management units and memory bus. In the third year, we will reference protocols of other sub-projects to complete the final detailed structure of memory system, and a built-in-self-test circuit and a built-in-self-repair circuit will be included. Moreover, we will focus on different memory demands for heterogeneous systems and construct memory compiler, so to complete the memory system.