On designing of 4-valued memory with double-gate TFT

標題:	On designing of 4-valued memory with double-gate TFT
作者:	Lee, CL Chern, HN Liao, MS Wang, HM 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	multi-valued logic;double-gate thin film transistor;SRAM;circuit design
公開日期:	1995
URI:	http://hdl.handle.net/11536/20013
ISBN:	0-7803-2764-0
ISSN:	0195-623X
期刊:	1995 25TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS
起始頁:	187
結束頁:	192
顯示於類別：	會議論文