Design of a CMOS T/R Switch With High Power Capability: Using Asymmetric Transistors

標題:	Design of a CMOS T/R Switch With High Power Capability: Using Asymmetric Transistors
作者:	Liu, Szu-Ling Wu, Meng-Hsiu Chin, Albert 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	BVdss;insertion loss;isolation;power-handling capability
公開日期:	1-十二月-2012
摘要:	A single-pole double-throw transmit/receive (T/R) switch has been realized by using both conventional and asymmetric MOSFETs in a standard 0.18 mu m CMOS technology. At 2.4 and 5.8 GHz, the asymmetric-transistor based T/R switch shows 2.7 dBm and 2.3 dBm improvements in measured 1 dB compression points (P(1 dB)s) than the conventional circuit of the same circuitry and layout, respectively. This switch also has good insertion losses of 0.62/0.7 and 0.94/1.2 dB for transmit-end/receive-end modes at 2.4 and 5.8 GHz, respectively.
URI:	http://dx.doi.org/10.1109/LMWC.2012.2227465 http://hdl.handle.net/11536/21301
ISSN:	1531-1309
DOI:	10.1109/LMWC.2012.2227465
期刊:	IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS
Volume:	22
Issue:	12
起始頁:	645
結束頁:	647
顯示於類別：	期刊論文

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