標題: 應用比例式記憶體之互補式金氧半改良式Hopfield類神經網路
THE DESIGN OF CMOS MODIFIED HOPFIELD NEURAL NETWORK WITH RATIO MEMORY
作者: 鄭秋宏
Cheng, Chiu-Hung
吳 重 雨
Prof. Chung-Yu Wu
電子研究所
關鍵字: 類神經網路;比例式記憶體;Hopfield;neural network;ratio memory
公開日期: 1996
摘要: 本論文之主旨在於利用"應用比例式記憶體之改良式Hopfield類神經 網路"來從事影像辨認的功能,並討論其中輸入訊號與回授訊號兩者之存 在時間與其相對大小之對於輸出結果所可能造成之影響。 在此電路 中,應用了一適當之四象限類比電流乘法器。而為解決其中因為加法所須 之電壓加法器之複雜度,改採用電流式之加法器;再經由一I-V轉換器將 之轉成電壓輸出。並開發一 二象限除法器,利用電晶體操作於linear region時,其電壓與電流可形成除法之關係;解決各個weight相加之後, 須轉成數個電流源以供給下一級的除法器當分母,所耗費之面積問題。 且利用比例式記憶體之特性,達到改善一般儲存記憶體對於其所儲存的 weight會隨時間而大幅衰減而需加入 refresh 電路的缺點;利用記憶各 個weight之間的相對關係,使得所記憶之資料,不會隨時間而快速的衰減 。 In this thesis, the modified Hopfield neural network with ratio memory is implemented in CMOS to recognize and classify the image patterns. In the implemented CMOS neural network, a CMOS analog four-quadrant currentmultiplier is used to perform the multiplication. A CMOS current summing circuitis used to perform the signal summation. Moreover, a new CMOS analog two- quadrant divider circuit is proposed. In the proposed CMOS divider, the drain-source voltage the PMOSFET operated in the linear region is proportional to the drain current of the PMOS device divided by the gate-source voltage. Thus, the divider can have a simple structure and large input/output signal range. The ideal modified Hopfield neural network to test the storage capacity and the storage time is simulated by Matlab software. On the other way, the storagecapacity and storage time of the real modified Hopfield is simulated by the HSPICE software, and the measurement of the chip will be discussed latter.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT850428117
http://hdl.handle.net/11536/61992
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