產生內嵌式系統程式碼時位址暫存器的配置

Abstract

近年來內嵌式系統（一個中央處理器搭配唯讀記體和隨機存取記憶體的設計方式，控制處理器的程式碼存在唯讀記憶體中）的設計很盛行。由於在晶片上的儲存空間有限，使得程式碼的大小成為一個很重要的議題。除了儲存空間的限制之外，程式碼的大小也影響了執行此程式碼時表現的效能。 在這篇論文中，我們提了一個演算法來減少程式碼中回圈部份程式碼的大小。所提的演算法可以得到在有限數目的位址暫存器的條件下，與不同數目位址暫存器對應的各個最佳位址暫存器的配置方式。從實驗的結果可以看出對某些程式碼而言其大小可以被明顯地縮小。但是對一些被公認驗證DSP的程式碼就沒有很明顯的效果，原因是那些被公認驗證DSP的程式碼已經是最佳化的結果了。在得到不同位址暫存器數目下的最佳位址暫存器分配方式之後，程式編譯器就可以利用它來有所選擇，產生執行起來效能較佳的內嵌式系統程式碼。

The embedded system design prevails in recent years. The code size becomes an important issue because of the limited storage capacity on the chip. Besides, it may affect the performance of the execution for the function. In this thesis, we propose an algorithm to reduce the code size in the loop segments. The proposed algorithm can find the optimal address register allocation for loop codes subject to the constraints on the number of address registers. The experimental results show significant reductions on the code size for some codes. However, the algorithm doesn’t improve the DSP’s benchmark circuits very much because those codes are already well written. The compiler can therefore use the technique to produce more efficient codes for the embedded systems. 2 Previous Work 5 2.1 The Address Generation Unit (AGU) 5 2.2 Researches on the Straight-line Code 7 2.3 Researches on the Loop Code 9 2.4 Conclusions and Critics 11 3 The Definition of the Problem 13 3.1 The Problem’s Definition 13 3.2 The Algorithm’s Assumptions 16 4 The Algorithm 17 4.1 The Access Graph 18 4.2 The Dependency Graph 19 4.3 The Operational Sequence 19 4.3.1 Find the Ideal AR Allocation 22 4.3.1.1 Initial Allocation 22 4.3.1.2 Build 0-Cost_loop Address Transition Graph (CATG) 22 4.3.1.3 Extract 0-Cost_iter Paths from the CATG 23 4.3.2 The Merging Process 28 4.4 After the Merging Process 31 5 The Experimental Result 33 6 The Conclusions and Future Work 39