標題: 高深寬比微結構模仁的製作程序的研究—利用矽基加工技術
Investigation of Fabricating Process for the Mold Insert with High Aspect Ratio Microstructures — Using the Silicon Processing Technology
作者: 張振銓
Chen Chuan Chang
陳仁浩
Ren Haw Chen
機械工程學系
關鍵字: 蝕刻;模仁;高深寬比;電鑄;導電性;基板;電阻值;摻雜;ICP;wet;dry;etching;molding;LIGA;insert;mold
公開日期: 2001
摘要: 本研究以製作高深寬比微結構模仁為目的,採用與半導體製程相容性極強之UV-LIGA的製作程序,利用矽<100>為載具,針對電鑄時會發生的鍍層缺陷問題,開發製作改良的導電性基板,且設計一系列實驗預測及印證在製作高深寬比微結構模仁時電鑄所發生的問題,並研究以及解決。主要的探討主題如下:(1)基板導電層製作與其電學特性,(2)結構層製作以及內應力,(3)光阻塗佈時之旋佈特性,(4)曝光條件以及光罩設計補償,(5)乾式及濕式蝕刻製程以及蝕刻阻擋層之製作,(6)導電性基板的電鑄特性之探討。 由實驗以及研究結果顯示: 1. 利用摻雜所製作的矽基化合物導電層基板對矽結構層之黏著性較金屬導電層對矽基板及矽結構層之黏著性為佳,但矽基化合物的體電阻以及面電阻係數較金屬導電層大,藉由控制摻雜磷的製程溫度與製程時間,得到與金屬導電層相同的電學特性。 2. 蝕刻製程上,光阻為濕式蝕刻之阻擋層,目的在製作乾式蝕刻之二氧化矽阻擋層。為了使微結構具備良好品質,必須精確掌握光罩之設計補償,以補償蝕刻時所造成之底切現象。此外在利用濕式蝕刻製作乾式蝕刻阻擋層時,必須考慮乾式蝕刻所需之蝕刻厚度,否則會因濕式蝕刻時之底切過大而造成乾式蝕刻阻擋層之尺寸誤差。 3. 在實際電鑄,摻雜磷之矽基導電性基板可獲得與金屬導電性基板同樣特性的微結構模仁。在使用KOH分離導電性基板以及電鑄微結構模仁時,利用矽基的導電性基板比金屬導電性基板少了一個製程步驟,可節省製程時間以及降低製程的複雜性。
This research is the fabricating process for the mold insert with high aspect ratio microstructures. We adopt the UV-LIGA process that reconciled with the semiconductor manufacturing process as our manufacturing process. Using <100> oriented silicon wafer, to aim at the defects that happened in electroforming microstructures, and to develop a new substrate with electric conductivity. Design a series of experiments to predict and solve the problems in manufacturing mold insert with high aspect ratio microstructures. The main investigation subjects are follows: (1) fabricating the substrate layer with electric conductivity, and its electric characteristics, (2) fabricating the structure layer, and investigating its stress, (3) spinning characteristics when spin photoresist, (4) exposure condition, and compensation design of masks, (5) fabricating the etching masks of dry & wet etching, (6) the characteristics of electroforming. From the results of experiments and researchs shows: 1. The adhesion between doped phosphorous silicon wafer and silicide is better than the adhesion between sputtered metals and silicide. By controlling the process temperature and process time, the doped phosphorous silicons have almost the same sheet resistance and bulk resistance as metal ones. 2. In the etching process, photoresist is the wet etching mask when fabricating dry etching mask of the ICP. In order to obtain good quality of the microstructure, when considerating the undercut of wet etching, we need to do the compensation design of masks. 3. We can obtain the nickel microstructure mold insert that have the good quality in reality electroforming by using doped phosphorous silicon wafer substrate.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT900489050
http://hdl.handle.net/11536/69167
顯示於類別:畢業論文