實現一個基於多關聯性的背景式數位校正之 十三位元每秒一億次取樣管線式類比數位轉換器

Abstract

隨著可攜式電子應用的蓬勃發展，降低電路的功率消耗成為非常重要的課題。在管線式類比數位轉換器中，最前端的Multiplying Digital-to-Analog Convertor(MDAC)需要達成最嚴峻的線性度、速度和雜訊的規格。在傳統的閉迴路(closed-loop)管線式類比數位轉換器架構中， MDAC電路需要一個高增益、高單增益頻寬的運算放大器(Operational Amplifier, OP)，這也同時意味著可觀的功率消耗。此外，在先進製程中。類比電路的設計遇到了許多難題，例如電晶體的本質增益(intrinsic gain)下降，供應電壓(supply voltage)的下降限制了訊號擺幅，無法以疊接(cascode)組態實現高增益，因此，如何設計一個高效能的運算放大器變成一個相當棘手的難題。相反的，數位電路隨著製程演進獲得相當多的好處，包含更高的操作速度，更少的功率消耗，以及更小的面積。因此，使用數位輔助類比(digital-assisted analog circuit)的設計概念，在先進製程中成為一個相當重要的研究方向。 為了大幅降低功率消耗，並且降低在先進製程下的設計難度，本篇論文中，以開迴路(open-Loop)架構取代傳統的閉迴路(closed-Loop)架構實現一個13-bit 100MS/s管線式類比數位轉換器中最前級的MDAC電路。使用開迴路架構的優點為適合操作在高速，且殘值放大器架構簡單、設計容易，並可以大幅降低功率消耗。因為開迴路架構產生的線性及非線性誤差，本篇論文則採用一種基於多關聯性的背景式數位校正(multi-correlation based digital background calibration)機制對誤差進行估測及校正。以數位電路輔助類比電路的設計概念，實現一個高效能的管線式類比數位轉換器。 本篇論文以TSMC 90-nm製程完成晶片設計與實現。靜態參數量測結果顯示，在正常模式下，DNL為-1.00LSB/+3.92LSB，INL為-194.74LSB/+184.36LSB。在校正模式下，DNL以及INL分別大幅度改善為-1.00LSB/+2.63LSB，-5.60LSB/+5.70LSB。動態參數量測結果顯示，校正前之ENOB=5.3bits。校正後，ENOB提升3.4bits至8.7bits。校正後效能明顯的改善但仍有改善空間。推測限制校正效能的原因有二個，第一個為設計考量不夠周全，造成實測之高階非線性誤差，超出本篇論文設計的可校正階數。第二個原因為校正級中MDAC電容的隨機誤差過大，造成校正級sub-DAC的解析度不足，大幅的限制住校正效能。

With the rapid growth of portable electronics applications, reducing the power consumption of the circuits becomes a very important issue. In the pipelined analog to digital converter (ADC), the front-end multiplying digital-to-analog convertor (MDAC) needs to meet the most stringent linearity, speed and noise requirements. In the traditional closed-loop pipeline ADC, the MDAC requires an operational amplifier (OP) with a high open-loop gain and a large unity-gain bandwidth, which consumes power. Moreover, analog circuit design encounters many challenges in advanced technology, such as decreased intrinsic gain and limited signal headroom due to reduced supply voltage. Consequently, how to design an OP that can achieve the stringent specifications becomes a very difficult challenge. On the contrary, digital circuits benefit from advanced technology for fast operation, lower power, and a smaller chip area. Consequently, the digital-assisted analog circuit design concept becomes an important research topic in advanced technology. This thesis proposes a 13-bit 100-MS/s pipelined ADC which replaces the conventional closed-loop residue amplifier with a simple open-loop one in the first pipelined stage. The advantages of using an open-loop residue amplifier include fast operation, signaificantly reduced power, and the easy design of the residual amplifier. The linear and 3rd order nonlinear errors induced by the open-loop residue amplifier is estimated and calibrated using the multi-correlation based digital background calibration. The thesis implements a high performance pipelined ADC by adopting the concept of digital-assist analog circuit design. The proposed pipelined ADC has been designed and fabricated in TSMC 90-nm CMOS process. The measurement results show that, the DNL and INL of the pipelined ADC without calibration are within -1.00/+3.92 LSB and -194.74/+184.36 LSB, and improved to -1.00/+2.63 LSB and -5.60/+5.70 LSB after calibration, respectively. The dynamic test results show the ENOB of thr pipelined ADC is improved from 5.3 bits to 8.7 bits with the calibration. 3.4 ENOB enhancement is achieved. The results show the significant improvement in performance after calibration but there is still room for improvement. There are two possible resons that cause the performance degradation. First, the high order which large than 5th order nonlinear errors excess the calibration range of this thesis. Second, the capacitor mismatch in sub-DAC of under calibration stage insufficient the resolution of DAC, dramatically limits on calibration performance.