A single chip microprocessor compatible digital 128-bit correlator design is implemented in 3 ¡im M^CMOS process. Full-custom design techniques are applied to achieve the best trade off among chip size, speed and power consumption. The chip is to be placed in a microprocessor based radio communication system. It marks the beginning of a synchronous data stream received from a very noisy channel by detecting the synchronization (sync) word. Two chips can be cascaded to make a 256-bit correlator. It is fully programmable by a microprocessor to set the number of tolerable errors in detection and to select the bits of the 128-bit (or 256-bit) data stream to be used in the correlation. The latter feature makes the correlator capable for use in detection of distributed sync words and PRBS generation. The silicon area of the chip and hence the chip cost is minimized by reducing the gate count in the logic design, by keeping the transistor sizes minimum without avoiding the timing specifications of the design and by a proper placement (floor plan) of the transistors on the silicon. The layouts are laid in a hierarchical manner. Unused areas are minimized and the layouts are designed in compact forms. During the layout design, charge sharing, body effect, latch-up, metal migration, noise and clock skew problems are considered. Mainly, the softwares. M agic, Spice, E sim and R nl are used for layout editing, timing and function simulations. These programs are run on SUN workstations under 4.3 BSD UNIX^ operating system.