Title:
Experimental benchmarking of CVD graphene for memory and interconnect applications
Experimental benchmarking of CVD graphene for memory and interconnect applications
Author(s)
Nashed Bassely Said, Ramy
Advisor(s)
Naeemi, Azad
Bakir, Muhannad S.
Vogel, Eric M.
Davis, Jeffrey A.
Catthoor, Francky
Bakir, Muhannad S.
Vogel, Eric M.
Davis, Jeffrey A.
Catthoor, Francky
Editor(s)
Collections
Supplementary to
Permanent Link
Abstract
CVD-grown graphene was studied as a potential candidate for memory as well as electrical interconnect applications. An average field-enhancement factor (β) of ~2.06 with a standard deviation of 0.33 was extracted using a modified Fowler-Nordheim equation for CVD-grown single layer graphene based on an MOS structure. This modest value solves the contradiction in prior experiments that reported a field enhancement factor of few thousands but only 30-40% improvement in the write voltage of floating gate memory devices. The experimentally extracted β value was used to drive higher-level circuit simulations on 64-bit NAND strings and it was shown that 2D NAND programming time and/or programming voltage can be suppressed to 10ns and 5V, respectively, based on a 65 nm process node. Furthermore, a simple two-step lithography process to fabricate graphene devices with mobilities up to ~9,500 cm2/V.s at a carrier concentration of 4x1012 cm-2 has been presented to assess the performance of graphene for interconnect applications. Even though the reported mobility is more than 2x higher than the average recorded mobility, MFP analysis shows that the MFP attained still needs to at least be doubled in order to achieve a significant improvement in the energy-delay product over copper interconnects. Better performance can be achieved by considering multilayer graphene instead of single layer graphene. An accurate method to determine the interlayer resistivity of multilayer graphene is proposed based on the direct measurement of the resistance at a mono-to-bi layer step and feeding the measured resistance to a distributed resistance model to extract the interlayer resistivity. The extracted values were used to analyze the performance of MLG interconnects in terms of interconnect delay, energy dissipation, and energy-delay product. The interlayer resistivity of CVD-grown AB-stacked bilayer graphene was found to be in the range of 50-140 Ω⋅m, which is two-five orders of magnitude larger than the previously reported values for AB-stacked graphite. On the other hand, twisted BLG shows 3-5x lower interlayer resistivity compared to AB-stacked BLG with the interlayer resistivity monotonically decreasing with increasing the twist angle. The total resistance of twisted BLG was found to be about one order of magnitude lower than its AB-stacked counterpart, leading to a lower delay and energy-delay product in twisted graphene.
Sponsor
Date Issued
2019-05-21
Extent
Resource Type
Text
Resource Subtype
Dissertation