Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage
- Author
- C ANGHEL, N HEFYENE, A IONESCU, Miguel Vermandel (UGent) , Benoit Bakeroot (UGent) , Jan Doutreloigne (UGent) , R GILLON, S FRERE, C MAIER and Y MOURIER
- Organization
Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-346429
- MLA
- ANGHEL, C., et al. “Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage.” Proceedings of the European Solid-State Device Research Conference, 2001, pp. 399–402.
- APA
- ANGHEL, C., HEFYENE, N., IONESCU, A., Vermandel, M., Bakeroot, B., Doutreloigne, J., … MOURIER, Y. (2001). Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage. Proceedings of the European Solid-State Device Research Conference, 399–402.
- Chicago author-date
- ANGHEL, C, N HEFYENE, A IONESCU, Miguel Vermandel, Benoit Bakeroot, Jan Doutreloigne, R GILLON, S FRERE, C MAIER, and Y MOURIER. 2001. “Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage.” In Proceedings of the European Solid-State Device Research Conference, 399–402.
- Chicago author-date (all authors)
- ANGHEL, C, N HEFYENE, A IONESCU, Miguel Vermandel, Benoit Bakeroot, Jan Doutreloigne, R GILLON, S FRERE, C MAIER, and Y MOURIER. 2001. “Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage.” In Proceedings of the European Solid-State Device Research Conference, 399–402.
- Vancouver
- 1.ANGHEL C, HEFYENE N, IONESCU A, Vermandel M, Bakeroot B, Doutreloigne J, et al. Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage. In: Proceedings of the European Solid-State Device Research Conference. 2001. p. 399–402.
- IEEE
- [1]C. ANGHEL et al., “Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage,” in Proceedings of the European Solid-State Device Research Conference, 2001, pp. 399–402.
@inproceedings{346429, author = {{ANGHEL, C and HEFYENE, N and IONESCU, A and Vermandel, Miguel and Bakeroot, Benoit and Doutreloigne, Jan and GILLON, R and FRERE, S and MAIER, C and MOURIER, Y}}, booktitle = {{Proceedings of the European Solid-State Device Research Conference}}, language = {{und}}, pages = {{399--402}}, title = {{Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage}}, year = {{2001}}, }