A 16-bit reconfigurable encryption processor for Pi-Cipher
- Author
- Mohamed El-Hadedy, Hristina Mihajloska, Danilo Gligoroski, Amit Kulkarni (UGent) , Dirk Stroobandt (UGent) and Kevin Skadron
- Organization
- Abstract
- This paper presents an improved hardware implementation of a 16-bit ARX (Add, Rotate, and Xor) engine for one of the CAESAR second-round competition candidates, Pi-Cipher, implemented on an FPGA. Pi-Cipher is a nonce-based authenticated encryption cipher with associated data. The security of the Pi-Cipher relies on an ARX based permutation function, which is denoted as a Pi-function. The proposed ARX engine has been implemented in just 266 slices, which includes the buffers of the input and the output. It can be clocked at 347 MHz. Also, in this paper, a message processor based on the proposed ARX engine is introduced. The message processor has been implemented in 1114 slices and it can be clocked at 250 MHz. The functionality of the proposed ARX engine was verified on the Xilinx Virtex-7. The new design of the ARX engine allows for almost four times speedup in performance while consuming only 17% larger area than previously published work. We extend our message processor implementation by using parametrized reconfiguration technique after which an area reduction of 27 slices is observed.
- Keywords
- FPGA, Authenticated encryption, CAESAR, Cryptographic competitions, π-Cipher, micro-reconfiguration, parameterized configuration, TLUT
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-7222721
- MLA
- El-Hadedy, Mohamed, et al. “A 16-Bit Reconfigurable Encryption Processor for Pi-Cipher.” 2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), IEEE xplore, 2016, pp. 162–71, doi:10.1109/IPDPSW.2016.27.
- APA
- El-Hadedy, M., Mihajloska, H., Gligoroski, D., Kulkarni, A., Stroobandt, D., & Skadron, K. (2016). A 16-bit reconfigurable encryption processor for Pi-Cipher. 2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 162–171. https://doi.org/10.1109/IPDPSW.2016.27
- Chicago author-date
- El-Hadedy, Mohamed, Hristina Mihajloska, Danilo Gligoroski, Amit Kulkarni, Dirk Stroobandt, and Kevin Skadron. 2016. “A 16-Bit Reconfigurable Encryption Processor for Pi-Cipher.” In 2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 162–71. Chicago, USA: IEEE xplore. https://doi.org/10.1109/IPDPSW.2016.27.
- Chicago author-date (all authors)
- El-Hadedy, Mohamed, Hristina Mihajloska, Danilo Gligoroski, Amit Kulkarni, Dirk Stroobandt, and Kevin Skadron. 2016. “A 16-Bit Reconfigurable Encryption Processor for Pi-Cipher.” In 2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 162–171. Chicago, USA: IEEE xplore. doi:10.1109/IPDPSW.2016.27.
- Vancouver
- 1.El-Hadedy M, Mihajloska H, Gligoroski D, Kulkarni A, Stroobandt D, Skadron K. A 16-bit reconfigurable encryption processor for Pi-Cipher. In: 2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW). Chicago, USA: IEEE xplore; 2016. p. 162–71.
- IEEE
- [1]M. El-Hadedy, H. Mihajloska, D. Gligoroski, A. Kulkarni, D. Stroobandt, and K. Skadron, “A 16-bit reconfigurable encryption processor for Pi-Cipher,” in 2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), Chicago, USA, 2016, pp. 162–171.
@inproceedings{7222721,
abstract = {{This paper presents an improved hardware implementation of a 16-bit ARX (Add, Rotate, and Xor) engine for one of the CAESAR second-round competition candidates, Pi-Cipher, implemented on an FPGA. Pi-Cipher is a nonce-based authenticated encryption cipher with associated data. The security of the Pi-Cipher relies on an ARX based permutation function, which is denoted as a Pi-function. The proposed ARX engine has been implemented in just 266 slices, which includes the buffers of the input and the output. It can be clocked at 347 MHz. Also, in this paper, a message processor based on the proposed ARX engine is introduced. The message processor has been implemented in 1114 slices and it can be clocked at 250 MHz. The functionality of the proposed ARX engine was verified on the Xilinx Virtex-7. The new design of the ARX engine allows for almost four times speedup in performance while consuming only 17% larger area than previously published work. We extend our message processor implementation by using parametrized reconfiguration technique after which an area reduction of 27 slices is observed.}},
author = {{El-Hadedy, Mohamed and Mihajloska, Hristina and Gligoroski, Danilo and Kulkarni, Amit and Stroobandt, Dirk and Skadron, Kevin}},
booktitle = {{2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW)}},
isbn = {{9781509036820}},
issn = {{2164-7062}},
keywords = {{FPGA,Authenticated encryption,CAESAR,Cryptographic competitions,π-Cipher,micro-reconfiguration,parameterized configuration,TLUT}},
language = {{eng}},
location = {{Chicago, USA}},
pages = {{162--171}},
publisher = {{IEEE xplore}},
title = {{A 16-bit reconfigurable encryption processor for Pi-Cipher}},
url = {{http://doi.org/10.1109/IPDPSW.2016.27}},
year = {{2016}},
}
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