Graduate Thesis Or Dissertation

 

Experimental verification of a mismatch-shaping DAC Public Deposited

Downloadable Content

Download PDF
https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/wp988n734

Descriptions

Attribute NameValues
Creator
Abstract
  • Delta-sigma data converters have gained popularity in both analog-to-digital and digital-to-analog converters (ADCs and DACs) due to their simplicity, high linearity and immunity to many analog circuit imperfections. These data converters include features such as oversampling, noise-shaping, and (historically) single-bit quantization. Single-bit converters are preferred for their inherent linearity. This is a feature which multibit converters cannot realize due to the unavoidable phenomenon of element mismatch. Because of this problem, multibit converters have been largely unexplored, and the market has seen few multibit commercial products. Earlier work has shown that multibit DACs constructed with unit elements can be applied in an architecture which shapes the spectrum of the noise caused by element mismatch. The basis of this thesis is the experimental verification of such a DAC. A Xilinx 4005 FPGA is utilized to implement a 3rd-order 4-bit delta-sigma modulator and the mismatch-shaping logic, while a custom IC consisting of 16 individually-controlled differential current sources implements the unit-element DAC. The final DAC achives a Spurious Free Dynamic Range (SFDR) of 96 dB at a sampling rate of 62.5 kHz.
Resource Type
Date Available
Date Issued
Degree Level
Degree Name
Degree Field
Degree Grantor
Commencement Year
Advisor
Committee Member
Academic Affiliation
Non-Academic Affiliation
Subject
Rights Statement
Publisher
Peer Reviewed
Language
Digitization Specifications
  • File scanned at 300 ppi (Monochrome) using Capture Perfect 3.0 on a Canon DR-9050C in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
Replaces

Relationships

Parents:

This work has no parents.

In Collection:

Items