Abstract
Due to their high performance, Reduced Instruction Set Computer (RISC) based microprocessors have been widely used in computing systems as well as embedded control and communication systems. The first and the most important step in designing a RISC microprocessor is to define the instruction set and its corresponding architecture. It will be inconvenient in terms of time and cost to verify an instruction set and its architecture through complete hardware realization. Therefore, a logic simulator for RISC microprocessor is highly desirable. This thesis studies the logic simulation of RISC microprocessors based on behavioral modeling approach. Many behavioral models for the components of RISC microprocessors, like ALU, multiplexer, memory, control unit, are proposed. A prototype, called LSRM (a Logic Simulator for RISC-based Microprocessor), is also designed and implemented in SUN/UNIX environment. LSRM consists of a graphical user interface and a simulator. The user interface is built on the X-window/Motif system while the simulator is implemented in C, Verilog and PLI. The system model adopted in this research is based on the DLX machine. However, substantial extension is made in order to satisfy as many applications as possible.
Jiang, Xiaohua (1993). LSRM - a tool for logic simulation of RISC-based microprocessor. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1993 -THESIS -J61.