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A high speed sequential decoderThe performance and theory of operation for the High Speed Hard Decision Sequential Decoder are delineated. The decoder is a forward error correction system which is capable of accepting data from binary-phase-shift-keyed and quadriphase-shift-keyed modems at input data rates up to 30 megabits per second. Test results show that the decoder is capable of maintaining a composite error rate of 0.00001 at an input E sub b/N sub o of 5.6 db. This performance has been obtained with minimum circuit complexity.
Document ID
19730011495
Acquisition Source
Legacy CDMS
Document Type
Technical Memorandum (TM)
Authors
Lum, H., Jr. (NASA Ames Research Center Moffett Field, CA, United States)
Date Acquired
September 2, 2013
Publication Date
December 1, 1972
Subject Category
Computers
Report/Patent Number
NASA-TM-X-62241
Accession Number
73N20222
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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