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A multiprocessor computer simulation model employing a feedback scheduler/allocator for memory space and bandwidth matching and TMR processingA computer simulation model for a multiprocessor computer is developed that is useful for studying the problem of matching multiprocessor's memory space, memory bandwidth and numbers and speeds of processors with aggregate job set characteristics. The model assumes an input work load of a set of recurrent jobs. The model includes a feedback scheduler/allocator which attempts to improve system performance through higher memory bandwidth utilization by matching individual job requirements for space and bandwidth with space availability and estimates of bandwidth availability at the times of memory allocation. The simulation model includes provisions for specifying precedence relations among the jobs in a job set, and provisions for specifying precedence execution of TMR (Triple Modular Redundant and SIMPLEX (non redundant) jobs.
Document ID
19750008178
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Bradley, D. B. (Auburn Univ. AL, United States)
Irwin, J. D. (Auburn Univ. AL, United States)
Date Acquired
September 3, 2013
Publication Date
December 1, 1974
Subject Category
Computer Programming And Software
Report/Patent Number
NASA-CR-120598
Accession Number
75N16250
Funding Number(s)
CONTRACT_GRANT: NAS8-26930
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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