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Design and implementation of a medium speed communications interface and protocol for a low cost, refreshed display computerThe design and implementation of hardware and software systems involved in using a 40,000 bit/second communication line as the connecting link between an IMLAC PDS 1-D display computer and a Univac 1108 computer system were described. The IMLAC consists of two independent processors sharing a common memory. The display processor generates the deflection and beam control currents as it interprets a program contained in the memory; the minicomputer has a general instruction set and is responsible for starting and stopping the display processor and for communicating with the outside world through the keyboard, teletype, light pen, and communication line. The processing time associated with each data byte was minimized by designing the input and output processes as finite state machines which automatically sequence from each state to the next. Several tests of the communication link and the IMLAC software were made using a special low capacity computer grade cable between the IMLAC and the Univac.
Document ID
19760009750
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Phyne, J. R.
(Houston Univ. TX, United States)
Nelson, M. D.
(Houston Univ. TX, United States)
Date Acquired
August 8, 2013
Publication Date
January 1, 1975
Publication Information
Publication: NASA. Langley Res. Center Appl. of Computer Graphics in Eng.
Subject Category
Computer Operations And Hardware
Accession Number
76N16838
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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