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Measurement of fault latency in a digital avionic mini processor, part 2The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are described. Several earlier programs were reprogrammed, expanding the instruction set to capitalize on the full power of the BDX-930 computer. As a final demonstration of fault coverage an extensive, 3-axis, high performance flght control computation was added. The stages in the development of a CPU self-test program emphasizing the relationship between fault coverage, speed, and quantity of instructions were demonstrated.
Document ID
19830008826
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Mcgough, J. (Bendix Corp. Teterboro, NJ, United States)
Swern, F. (Bendix Corp. Teterboro, NJ, United States)
Date Acquired
September 4, 2013
Publication Date
January 1, 1983
Subject Category
Mathematical And Computer Sciences (General)
Report/Patent Number
NAS 1.26:3651
NASA-CR-3651
Accession Number
83N17097
Funding Number(s)
CONTRACT_GRANT: NAS1-15946
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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