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VLSI architectures for computing multiplications and inverses in GF(2-m)Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
Document ID
19840005338
Acquisition Source
Legacy CDMS
Document Type
Other
Authors
Wang, C. C.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Truong, T. K.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Shao, H. M.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Deutsch, L. J.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Omura, J. K.
(California Univ. Los Angeles, United States)
Reed, I. S.
(Univ. of Southern California)
Date Acquired
August 12, 2013
Publication Date
November 15, 1983
Publication Information
Publication: The Telecommun. and Data Acquisition Rept.
Subject Category
Numerical Analysis
Accession Number
84N13406
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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