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Strategies for concurrent processing of complex algorithms in data driven architecturesPerformance modeling and performance enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures are discussed. Applications include real-time implementation of control and signal processing algorithms where performance is required to be highly predictable. The mapping of algorithms onto the specified class of data flow architectures is realized by a marked graph model called algorithm to architecture mapping model (ATAMM). Performance measures and bounds are established. Algorithm transformation techniques are identified for performance enhancement and reduction of resource (computing element) requirements. A systematic design procedure is described for generating operating conditions for predictable performance both with and without resource constraints. An ATAMM simulator is used to test and validate the performance prediction by the design procedure. Experiments on a three resource testbed provide verification of the ATAMM model and the design procedure.
Document ID
19910011082
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Som, Sukhamoy (Old Dominion Univ. Norfolk, VA, United States)
Stoughton, John W. (Old Dominion Univ. Norfolk, VA, United States)
Mielke, Roland R. (Old Dominion Univ. Norfolk, VA, United States)
Date Acquired
September 6, 2013
Publication Date
October 1, 1990
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
NAS 1.26:187450
NASA-CR-187450
Accession Number
91N20395
Funding Number(s)
CONTRACT_GRANT: NAG1-683
PROJECT: RTOP 590-32-31-01
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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