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Method for producing a hybridization of detector array and integrated circuit for readoutA process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.
Document ID
19940006201
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Fossum, Eric R.
(Jet Propulsion Lab. California Inst. of Tech., Pasadena., United States)
Grunthaner, Frank J.
(Jet Propulsion Lab. California Inst. of Tech., Pasadena., United States)
Date Acquired
August 16, 2013
Publication Date
August 17, 1993
Subject Category
Electronics And Electrical Engineering
Accession Number
94N10656
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
NASA-CASE-NPO-18062-1-CU|US-PATENT-5,236,871
Patent Application
US-PATENT-APPL-SN-877966
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