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Design and test of field programmable gate arrays in space applicationsField Programmable Gate Arrays (FPGAU's) offer substantial benefits in terms of flexibility and design integration. In addition to qualifying this device for space applications by establishing its reliability and evaluating its sensitivity to radiation, screening the programmed devices with Automatic Test Equipment (ATE) and functional burn-in presents an interesting challenge. This paper presents a review of the design, qualification, and screening cycle employed for FPGA designs in a space program, and demonstrates the need for close interaction between design and test engineers.
Document ID
19940017237
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Mckerracher, Priscilla L. (Johns Hopkins Univ. Laurel, MD, United States)
Cain, Russel P. (Johns Hopkins Univ. Laurel, MD, United States)
Barnett, Jon C. (Johns Hopkins Univ. Laurel, MD, United States)
Green, William S. (Johns Hopkins Univ. Laurel, MD, United States)
Kinnison, James D. (Johns Hopkins Univ. Laurel, MD, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1992
Publication Information
Publication: Idaho Univ., The 1992 4th NASA SERC Symposium on VLSI Design
Subject Category
Computer Programming And Software
Accession Number
94N21710
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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