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Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processorsIn a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.
Document ID
19950010985
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Fijany, Amir (Jet Propulsion Lab. California Inst. of Tech., Pasadena, CA., United States)
Bejczy, Antal K. (Jet Propulsion Lab. California Inst. of Tech., Pasadena, CA., United States)
Date Acquired
August 16, 2013
Publication Date
November 1, 1994
Subject Category
Computer Operations And Hardware
Accession Number
95N17400
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-PATENT-5,361,367|NASA-CASE-NPO-17632-1-CU
Patent Application
US-PATENT-APPL-SN-712796

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