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Implementing a Digital Phasemeter in an FPGAFirmware for implementing a digital phasemeter within a field-programmable gate array (FPGA) has been devised. In the original application of this firmware, the phase that one seeks to measure is the difference between the phases of two nominally-equal-frequency heterodyne signals generated by two interferometers. In that application, zero-crossing detectors convert the heterodyne signals to trains of rectangular pulses, the two pulse trains are fed to a fringe counter (the major part of the phasemeter) controlled by a clock signal having a frequency greater than the heterodyne frequency, and the fringe counter computes a time-averaged estimate of the difference between the phases of the two pulse trains. The firmware also does the following: Causes the FPGA to compute the frequencies of the input signals; Causes the FPGA to implement an Ethernet (or equivalent) transmitter for readout of phase and frequency values; and Provides data for use in diagnosis of communication failures. The readout rate can be set, by programming, to a value between 250 Hz and 1 kHz. Network addresses can be programmed by the user.
Document ID
20080048141
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other - NASA Tech Brief
External Source(s)
http://www.techbriefs.com/component/content/article/3187
Authors
Rao, Shanti R. (California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 24, 2013
Publication Date
September 1, 2008
Publication Information
Publication: NASA Tech Briefs, September 2008
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
NPO-45575
Distribution Limits
Public
Copyright
Public Use Permitted.

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