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Radiation tolerant combinational logic cellA system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.
Document ID
20090042988
Acquisition Source
Goddard Space Flight Center
Document Type
Other - Patent
Authors
Maki, Gary R.
Gambles, Jody W.
Whitaker, Sterling
Date Acquired
August 24, 2013
Publication Date
February 10, 2009
Subject Category
Electronics And Electrical Engineering
Funding Number(s)
CONTRACT_GRANT: NNG04GE96G
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-Patent-7,489,538
Patent Application
US-Patent-Appl-SN-11/527,375
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