SEE Tolerant Self-Calibrating Simple Fractional-N PLLWe show a reliable on-chip clock multiplier for SEE testing or RHBD applications. Fine control of clock frequency is provided without complex delta-sigma schemes. Conflicts that can occur with voted PLLs are discussed, and how to avoid them.
Document ID
20100017003
Acquisition Source
Johnson Space Center
Document Type
Conference Paper
Authors
Shuler, Robert L. (NASA Johnson Space Center Houston, TX, United States)
Chen, Li (Saskatchewan Univ. Saskatoon, Saskatchewan, Canada)