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SEE Tolerant Self-Calibrating Simple Fractional-N PLLWe show a reliable on-chip clock multiplier for SEE testing or RHBD applications. Fine control of clock frequency is provided without complex delta-sigma schemes. Conflicts that can occur with voted PLLs are discussed, and how to avoid them.
Document ID
20100017003
Acquisition Source
Johnson Space Center
Document Type
Conference Paper
Authors
Shuler, Robert L.
(NASA Johnson Space Center Houston, TX, United States)
Chen, Li
(Saskatchewan Univ. Saskatoon, Saskatchewan, Canada)
Date Acquired
August 24, 2013
Publication Date
April 12, 2010
Subject Category
Computer Programming And Software
Report/Patent Number
JSC-CN-20199
Meeting Information
Meeting: Single Event Effects Symposium
Location: San Diego, CA
Country: United States
Start Date: April 12, 2010
End Date: April 14, 2010
Sponsors: NASA Goddard Space Flight Center
Funding Number(s)
WBS: WBS 432938.09.01.05.03.31
Distribution Limits
Public
Copyright
Public Use Permitted.
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