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High-Voltage-Input Level Translator Using Standard CMOSproposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output
Document ID
20110011971
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other - NASA Tech Brief
Authors
Yager, Jeremy A.
(California Inst. of Tech. Pasadena, CA, United States)
Mojarradi, Mohammad M.
(California Inst. of Tech. Pasadena, CA, United States)
Vo, Tuan A.
(California Inst. of Tech. Pasadena, CA, United States)
Blalock, Benjamin J.
(Tennessee Univ. Knoxville, TN, United States)
Date Acquired
August 25, 2013
Publication Date
April 1, 2011
Publication Information
Publication: NASA Tech Briefs, April 2011
Subject Category
Technology Utilization And Surface Transportation
Report/Patent Number
NPO-45762
Distribution Limits
Public
Copyright
Public Use Permitted.
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