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Hardware Implementation of Lossless Adaptive Compression of Data From a Hyperspectral ImagerEfficient onboard data compression can reduce the data volume from hyperspectral imagers on NASA and DoD spacecraft in order to return as much imagery as possible through constrained downlink channels. Lossless compression is important for signature extraction, object recognition, and feature classification capabilities. To provide onboard data compression, a hardware implementation of a lossless hyperspectral compression algorithm was developed using a field programmable gate array (FPGA). The underlying algorithm is the Fast Lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral- Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), p. 26 with the modification reported in Lossless, Multi-Spectral Data Comressor for Improved Compression for Pushbroom-Type Instruments (NPO-45473), NASA Tech Briefs, Vol. 32, No. 7 (July 2008) p. 63, which provides improved compression performance for data from pushbroom-type imagers. An FPGA implementation of the unmodified FL algorithm was previously developed and reported in Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System (NPO-46867), NASA Tech Briefs, Vol. 36, No. 5 (May 2012) p. 42. The essence of the FL algorithm is adaptive linear predictive compression using the sign algorithm for filter adaption. The FL compressor achieves a combination of low complexity and compression effectiveness that exceeds that of stateof- the-art techniques currently in use. The modification changes the predictor structure to tolerate differences in sensitivity of different detector elements, as occurs in pushbroom-type imagers, which are suitable for spacecraft use. The FPGA implementation offers a low-cost, flexible solution compared to traditional ASIC (application specific integrated circuit) and can be integrated as an intellectual property (IP) for part of, e.g., a design that manages the instrument interface. The FPGA implementation was benchmarked on the Xilinx Virtex IV LX25 device, and ported to a Xilinx prototype board. The current implementation has a critical path of 29.5 ns, which dictated a clock speed of 33 MHz. The critical path delay is end-to-end measurement between the uncompressed input data and the output compression data stream. The implementation compresses one sample every clock cycle, which results in a speed of 33 Msample/s. The implementation has a rather low device use of the Xilinx Virtex IV LX25, making the total power consumption of the implementation about 1.27 W.
Document ID
20120010432
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other - NASA Tech Brief
External Source(s)
http://www.techbriefs.com/component/content/article/13865
Authors
Keymeulen, Didlier (California Inst. of Tech. Pasadena, CA, United States)
Aranki, Nazeeh I. (California Inst. of Tech. Pasadena, CA, United States)
Klimesh, Matthew A. (California Inst. of Tech. Pasadena, CA, United States)
Bakhshi, Alireza (B and A Engineers Ltd. United States)
Date Acquired
August 26, 2013
Publication Date
June 1, 2012
Publication Information
Publication: NASA Tech Briefs, June 2012
Subject Category
Man/System Technology And Life Support
Report/Patent Number
NPO-47103
Distribution Limits
Public
Copyright
Public Use Permitted.

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IDRelationTitle20120010415Collected WorksNASA Tech Briefs, June 2012
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