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Design for Review - Applying Lessons Learned to Improve the FPGA Review ProcessFlight Field Programmable Gate Array (FPGA) designs are required to be independently reviewed. This paper provides recommendations to Flight FPGA designers to properly prepare their designs for review in order to facilitate the review process, and reduce the impact of the review time in the overall project schedule.
Document ID
20140017835
Acquisition Source
Goddard Space Flight Center
Document Type
Conference Paper
Authors
Figueiredo, Marco A. (Orbital Sciences Corp. Greenbelt, MD, United States)
Li, Kenneth E. (NASA Goddard Space Flight Center Greenbelt, MD United States)
Date Acquired
December 30, 2014
Publication Date
August 29, 2014
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GSFC-E-DAA-TN15801
Meeting Information
Meeting: Single Event Effect (SEE) Symposium and Military Aerospace Programmable Logic Devices (MAPLD) Conference
Location: La Jolla, CA
Country: United States
Start Date: May 19, 2014
End Date: May 22, 2014
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
Process Improvement
Field Programmable Gate Array (FPGA)
Flight Design Reviews

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