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Fault-Tolerant Self-Stabilizing Distributed Clock Synchronization Protocol for Arbitrary DigraphsA self-stabilizing network in the form of an arbitrary, non-partitioned digraph includes K nodes having a synchronizer executing a protocol. K-1 monitors of each node may receive a Sync message transmitted from a directly connected node. When the Sync message is received, the logical clock value for the receiving node is set to between 0 and a communication latency value (gamma) if the clock value is less than a minimum event-response delay (D). A new Sync message is also transmitted to any directly connected nodes if the clock value is greater than or equal to both D and a graph threshold (T(sub S)). When the Sync message is not received the synchronizer increments the clock value if the clock value is less than a resynchronization period (P), and resets the clock value and transmits a new Sync message to all directly connected nodes when the clock value equals or exceeds P.
Document ID
20150003361
Acquisition Source
Headquarters
Document Type
Other - Patent
Authors
Malekpour, Mahyar R.
Date Acquired
March 20, 2015
Publication Date
October 14, 2014
Subject Category
Computer Programming And Software
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-Patent-8,861,552
Patent Application
US-Patent-Appl-SN-13/364,814
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