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Reliable Design Versus TrustThis presentation focuses on reliability and trust for the users portion of the FPGA design flow. It is assumed that the manufacturer prior to hand-off to the user tests FPGA internal components. The objective is to present the challenges of creating reliable and trusted designs. The following will be addressed: What makes a design vulnerable to functional flaws (reliability) or attackers (trust)? What are the challenges for verifying a reliable design versus a trusted design?
Document ID
20160010637
Acquisition Source
Goddard Space Flight Center
Document Type
Presentation
Authors
Berg, Melanie
(ASRC Federal Space and Defense Greenbelt, MD, United States)
LaBel, Kenneth A.
(NASA Goddard Space Flight Center Greenbelt, MD United States)
Date Acquired
August 30, 2016
Publication Date
August 23, 2016
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GSFC-E-DAA-TN34839
2016-561-NEPP
Meeting Information
Meeting: Field Programmable Gate Array Symposium
Location: Chantilly, VA
Country: United States
Start Date: August 23, 2016
Sponsors: National Reconnaissance Office
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
Field Programmable Gate Aray (FPGA)
security trust verification
reliability
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