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A new processor architecture exploiting ILP with a reduced instruction word
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Legat, Jean-Didier
[UCL]
Petit, Laurent
[UCL]
Petit, Laurent
[UCL]
| Document type | Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection |
|---|---|
| Publication date | 1998 |
| Language | Anglais |
| Conference | "IEE Colloquium on High Performance Architectures for real-time image processing", London (UK) (du 12/02/1998 au 12/02/1998) |
| Peer reviewed | yes |
| Host document | "Proc. of IEE Colloquium on High Performance Architectures for real-time image processing"- p. 2.1-2.5 |
| Affiliation | UCL - FSA/ELEC - Département d'électricité |
| Links |
| Bibliographic reference | Legat, Jean-Didier ; Petit, Laurent. A new processor architecture exploiting ILP with a reduced instruction word.IEE Colloquium on High Performance Architectures for real-time image processing (London (UK), du 12/02/1998 au 12/02/1998). In: Proc. of IEE Colloquium on High Performance Architectures for real-time image processing, 1998, p. 2.1-2.5 |
|---|---|
| Permanent URL | http://hdl.handle.net/2078.1/102432 |