Compact On-Wafer Test Structures for Device RF Characterization

The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50-μm-pitch RF probes. It is shown that by using these new test structures, the layoutgeometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100–150 μm-pitch RF probes. 50-μm-pitch de-embedding structures have been implemented on 0.18-μm RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of traprich SOI substrates is analyzed under small- and largesignal conditions.