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A 2.24-pJ/bit 2.5-Gb/s UWB receiver in 28-nm FDSOI CMOS for low-energy chip-to-chip communications

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Gimeno Gasca, Cecilia [UCL] Flandre, Denis [UCL] Schramme, Maxime [UCL] Frenkel, Charlotte [UCL] Bol, David [UCL]

Chip-to-chip communications in high-performance applications such as server racks rely on wireline serial links. In this paper, we present a compact ultra-wideband receiver front-end in 28-nm FDSOI CMOS technology as a wireless interconnect alternative for low-energy and broadcast communications. It is based on binary pulse position modulation without guard interval using two periods of a 10-GHz carrier to reach 2.5-Gb/s datarate over distances >20 cm. The proposed receiver occupies 0.3 mm2 (including decoupling capacitors) and consumes only 5.6 mW which results in an energy of 2.24 pJ/bit.

Document type Article de périodique (Journal article) – Article de recherche
Access type Accès libre
Publication date 2020
Language Anglais
Journal information "A E Ue: International Journal of Electronics and Communication" - Vol. 114, no. 152996, p. 8 (2020)
Peer reviewed yes
Publisher Urban und Fischer Verlag (Jena)
issn 1434-8411
Publication status Publié
Affiliation UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Keywords Chip-to-chip; UWB; ; Non-coherent; ; Receiver; ; Wireless communications
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Bibliographic reference Gimeno Gasca, Cecilia ; Flandre, Denis ; Schramme, Maxime ; Frenkel, Charlotte ; Bol, David. A 2.24-pJ/bit 2.5-Gb/s UWB receiver in 28-nm FDSOI CMOS for low-energy chip-to-chip communications. In: A E Ue: International Journal of Electronics and Communication, Vol. 114, no. 152996, p. 8 (2020)
Permanent URL http://hdl.handle.net/2078.1/223380